1. Field of the Invention
This invention relates to timing circuitry and, more particularly, to methods and apparatus for controlling the timing of data output enable signals.
2. History of the Prior Art
A large percentage of the data processing chips which are sold commercially today utilize an enable signal to drive data to the output terminals. The output enable signals are utilized in order to precisely determine the time at which any particular chip provides output signals so that, for example, a plurality of chips will not be providing signals to the same destination at the same time. In all known prior art arrangements, the output enable signal is an asynchronous input signal, a signal which is not sampled by the system clock. The result is that the output is turned on as soon as possible after the enable signal is received and is turned off as soon as possible after the enable signal is removed.
The actual time at which a chip turns on and off in response to the application and removal of the output enable signal depends upon the propagation time within the particular chip. In general, the time may vary by a very large amount for any particular chip. Consequently, it is necessary in most prior art circuits operating at high clock frequencies to provide a significant amount of clock time between enable signals so that two individual sources of data will not both be driving data onto a data bus simultaneously. This provision of time between the end of one enable signal and the beginning of the next (so called dead cycles) to assure that there is no conflict between output enable signals slows the computer system significantly. Moreover, the synchronization of the different output enable signals to assure an appropriate interval for the dead cycle so that the enable signals occur at the correct time is quite difficult.